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19-3505; Rev 0; 11/04
KIT ATION EVALU ABLE AVAIL
Low-Dropout, Wide-Input-Voltage, Step-Down Controllers
General Description Features
Low Dropout with >99.5% Duty Cycle Lossless High-Side Current Limit Wide 4.5V to 28V Input Range Dynamic Output Voltage Adjustment with Adjustable Offset (MAX8597) Remote Voltage Sensing for Both Positive and Negative Rails (MAX8597) Tracking Output Through REFIN (MAX8597) Adjustable Switching Frequency from 200kHz to 1.4MHz Adjustable Soft-Start Prebias Startup Enable and Power-OK (MAX8598/MAX8599) for Flexible Sequencing 25MHz Error Amplifier Adjustable Hiccup Current Limit for Output Short-Circuit Protection Output Overvoltage Protection (MAX8599) Small, Low-Profile Thin QFN Package
MAX8597/MAX8598/MAX8599
The MAX8597/MAX8598/MAX8599 voltage-mode PWM step-down controllers are designed to operate from a 4.5V to 28V input supply and generate output voltages down to 0.6V. A proprietary switching algorithm stretches the duty cycle to >99.5% for low-dropout design. Unlike conventional step-down regulators using a pchannel high-side MOSFET to achieve high duty cycle, the MAX8597/MAX8598/MAX8599 drive n-channel MOSFETs resulting in high efficiency and high-currentcapability designs. The MAX8597 is available in a 20-pin thin QFN package and is designed for applications that use an analog signal to control the output voltage with an adjustable offset, such as DC fan-speed control. This is achieved with an internal uncommitted operational amplifier. The MAX8597 is also targeted for tracking output-voltage applications for chipsets, ASIC and DSP cores, and I/O supplies. The MAX8598/MAX8599 are available in a 16pin thin QFN package and do not have the uncommitted operational amplifier, reference input, and reference output, but offer an open-drain, power-OK output. The MAX8597/MAX8598/MAX8599 allow startup with prebias voltage on the output for applications where a backup supply or a tracking device may charge the output capacitor before the MAX8597/MAX8598/ MAX8599 are enabled. In addition, the MAX8599 features output overvoltage protection. These controllers also feature lossless high-side peak inductor current sensing, adjustable current limit, and hiccup-mode short-circuit protection. Switching frequency is set with an external resistor from 200kHz to 1.4MHz. This wide frequency range combined with a wide-bandwidth error amplifier enables the loop compensation scheme to give the user ample flexibility to optimize for cost, size, and efficiency.
Ordering Information
PART TEMP RANGE PIN-PACKAGE 20 Thin QFN 4mm x 4mm (T2044-3) 16 Thin QFN 4mm x 4mm (T1644-4) 16 Thin QFN 4mm x 4mm (T1644-4)
MAX8597ETP+ -40C to +85C MAX8598ETE+ -40C to +85C MAX8599ETE+ -40C to +85C
+Denotes lead-free package.
Pin Configurations
PGND 12 BST TOP VIEW DH 15 ILIM FREQ AOUT AINAIN+ 16 17 18 19 20 1 AVL 2 REFIN 3 GND 4 SS 5 FB 14 13 11 10 9 VL V+ REFOUT EN COMP DL 8 7 6 LX
Applications
Nonisolated Power Modules Variable-Speed DC Fan Power Supplies (MAX8597) Tracking Power Supplies (MAX8597) Chipset Power Supplies
MAX8597
THIN QFN 4mm x 4mm
Pin Configurations continued at end of data sheet ________________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
Low-Dropout, Wide-Input-Voltage, Step-Down Controllers MAX8597/MAX8598/MAX8599
ABSOLUTE MAXIMUM RATINGS
V+, ILIM to GND .....................................................-0.3V to +30V AVL, VL to GND........................................................-0.3V to +6V PGND to GND .......................................................-0.3V to +0.3V FB, EN, POK, AIN-, AIN+, REFIN to GND ................-0.3V to +6V AOUT, REFOUT, FREQ, SS, COMP to GND .....................................................-0.3V to (VAVL + 0.3V) BST to GND ............................................................-0.3V to +36V DH to LX ....................................................-0.3V to (VBST + 0.3V) LX to GND ........................-2V (-2.5V for less than 50ns) to +30V LX to BST..................................................................-6V to +0.3V DL to PGND.................................................-0.3V to (VVL + 0.3V) Continuous Power Dissipation 16- or 20-Pin Thin QFN Up to +70C (derate 16.9mW/C above +70C)........1349mW Operating Temperature Range ...........................-40C to +85C Junction Temperature ......................................................+150C Storage Temperature Range .............................-65C to +150C Lead Temperature (soldering, 10s) .................................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VV+ = VVL = VAVL = VEN = VREFIN = 5V, VBST = 6V, VLX = 1V, CVL = 4.7F, CREFOUT = 1F, VAIN- = VAOUT, VAIN+ = 2.5V, VILIM = VLX - 0.2V, VFB = 0.65V, GND = PGND = 0V, CSS = 0.01F, RFREQ = 20k, TA = 0C to +85C, typical values are at TA = +25C, unless otherwise noted.)
PARAMETER GENERAL V+ Operating Range V+/VL Operating Range V+ Operating Supply Current V+ Standby Supply Current VL REGULATOR Output Voltage VL Undervoltage-Lockout Trip Level Thermal Shutdown REFERENCE (MAX8597 only) REFOUT Output Voltage REFOUT Load Regulation REFOUT Internal Discharge Switch On-Resistance ILIM Sink Current Comparator Input Offset Voltage Error SOFT-START Soft-Start Source Current Soft-Start Sink Current FREQUENCY RFREQ = 100k Frequency RFREQ = 20.0k RFREQ = 14.3k 150 800 1100 200 1000 1400 240 1200 1700 kHz VSS = 100mV VSS = (0.6V or VREFIN) 3 3 5 5 7 7 A A IREFOUT = 150A, VV+ = VVL = 4.5V or 5.5V IREFOUT = 10A to 1mA During VL UVLO 15 2.49 2.50 2.51 10 V mV 5.5V < VV+ < 28V, 1mA < ILOAD < 35mA Rising edge, typical hysteresis = 460mV Rising temperature, typical hysteresis = 10C 4.7 4.05 5.0 4.2 +160 5.3 4.35 V V C V+ = VL VV+ = 12V, VL unloaded, no MOSFETs connected, VFB = 0V VV+ = 12V, VL unloaded, VFB = 0V 5.5 4.5 3.4 2.0 28.0 5.5 5.0 V V mA mA CONDITIONS MIN TYP MAX UNITS
CURRENT-LIMIT COMPARATOR (all current limits are tested at VV+ = VVL = 4.5V and 5.5V) 1.8V < VLX < 28V, VBST = VLX + 5V VLX = 28V, VBST = VLX + 5V 180 -10 200 220 +10 A mV
2
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Low-Dropout, Wide-Input-Voltage, Step-Down Controllers
ELECTRICAL CHARACTERISTICS (continued)
(VV+ = VVL = VAVL = VEN = VREFIN = 5V, VBST = 6V, VLX = 1V, CVL = 4.7F, CREFOUT = 1F, VAIN- = VAOUT, VAIN+ = 2.5V, VILIM = VLX - 0.2V, VFB = 0.65V, GND = PGND = 0V, CSS = 0.01F, RFREQ = 20k, TA = 0C to +85C, typical values are at TA = +25C, unless otherwise noted.)
PARAMETER DH Minimum Off-Time DH Minimum On-Time FB ERROR AMPLIFIER FB Input Bias Current FB Input Voltage Set Point FB Offset Error Error-Amp Open-Loop Voltage Gain Slew Rate Over load and line VREFIN = 1.25V and 2.5V, measured with respect to REFIN VCOMP = 1.2V to 2.4V CLOAD = 80pF RLOAD = 100k RLOAD = 10k VAIN+ = 2.5V, VAIN- = (VAIN+ - 100mV), ISOURCE = 100A VAIN+ = 2.5V, VAIN- = (VAIN+ + 100mV), ISINK = 100A 1.5 CLOAD = 10pF, RLOAD = 10k to 100k CLOAD = 100pF, RLOAD = 10k to 100k CLOAD = 100pF VCM = 1.25V and 2.5V -3 -10 +0.50 75 +80 +40 3.5 +3 +10 VAVL 2.0 VAVL 20mV 20 0.594 +10 72 90 18 90 70 0.600 100 0.606 -10 nA V mV dB V/s CONDITIONS MIN 180 TYP 200 115 MAX 220 140 UNITS ns ns
MAX8597/MAX8598/MAX8599
UNCOMMITTED OPERATIONAL AMPLIFIER (MAX8597 only) Open-Loop Voltage Gain (AVOL) Output-Voltage Swing High Output-Voltage Swing Low Unity-Gain BW Phase Margin Slew Rate Input Offset Voltage Input Leakage Current Input Common-Mode Range (CMVR) Common-Mode Rejection Ratio (CMRR) DRIVERS DH, DL Break-Before-Make Time DH On-Resistance in Low State DH On-Resistance in High State DL On-Resistance in Low State DL On-Resistance in High State BST Bias Current LX Bias Current BST/LX Leakage Current LOGIC INPUTS (EN) Input Low Level Input High Level Input Bias Current 4.5V < VVL = VV+ = VAVL < 5.5V 4.5V < VVL = VV+ = VAVL < 5.5V VVL = VV+ = VAVL = 5.5V, VEN = 0 to 5.5V 2.40 -1 1.14 1.73 +1 0.80 V V A CLOAD = 2000pF VBST - VLX = 5V VBST - VLX = 5V VVL = VV+ = 5V VVL = VV+ = 5V VBST = 33V, VLX = 28V, VEN = 0V VBST = 33V, VLX = 28V, VEN = 0V VBST = VLX = 28V, VEN = 0V 20 1.0 1.5 0.45 1.3 230 -230 2.5 3.3 1.0 2.5 520 -520 50 ns A A A dB V mV MHz Degrees V/s mV nA V dB
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3
Low-Dropout, Wide-Input-Voltage, Step-Down Controllers MAX8597/MAX8598/MAX8599
ELECTRICAL CHARACTERISTICS (continued)
(VV+ = VVL = VAVL = VEN = VREFIN = 5V, VBST = 6V, VLX = 1V, CVL = 4.7F, CREFOUT = 1F, VAIN- = VAOUT, VAIN+ = 2.5V, VILIM = VLX - 0.2V, VFB = 0.65V, GND = PGND = 0V, CSS = 0.01F, RFREQ = 20k, TA = 0C to +85C, typical values are at TA = +25C, unless otherwise noted.)
PARAMETER REFIN INPUT (MAX8597 only) REFIN Input Voltage Range REFIN Dual ModeTM Threshold REFIN Input Bias Current Upper FB Fault Threshold (OV) Lower FB Fault Threshold (UV) VREFIN = 1.25V or 2.5V Rising edge, hysteresis = 15mV (MAX8599 only) Falling edge, hysteresis = 15mV 0 VAVL 1.0 -250 115 67 117 70 2.75 VAVL 0.5 +250 120 73 V V nA % % Clock cycles 90 0.4 5 % V A CONDITIONS MIN TYP MAX UNITS
OV AND UV FAULT COMPARATORS
POWER-OK OUTPUT (POK) (MAX8598/MAX8599 only) POK Delay Lower FB POK Threshold POK Output Low Level POK Output High Leakage For both FB rising and falling edges FB falling, hysteresis = 20mV ISINK = 2mA VPOK = 5.5V 85 8 88
ELECTRICAL CHARACTERISTICS
(VV+ = VVL = VAVL = VEN = VREFIN = 5V, VBST = 6V, VLX = 1V, CVL = 4.7F, CREFOUT = 1F, VAIN- = VAOUT, VAIN+ = 2.5V, VILIM = VLX - 0.2V, VFB = 0.65V, GND = PGND = 0V, CSS = 0.01F, RFREQ = 20k, TA = -40C to +85C, typical values are at TA = +25C, unless otherwise noted.) (Note 1)
PARAMETER GENERAL V+ Operating Range V+/VL Operating Range V+ Operating Supply Current VL REGULATOR Output Voltage VL Undervoltage-Lockout Trip Level REFERENCE (MAX8597 only) REFOUT Output Voltage REFOUT Load Regulation ILIM Sink Current Comparator Input Offset Voltage Error SOFT-START Soft-Start Source Current Soft-Start Sink Current VSS = 100mV VSS = (0.6V or VREFIN) 3 3 7 7 A A IREFOUT = 150A, VV+ = VVL = 4.5V or 5.5V IREFOUT = 10A to 1mA VILIM = VLX - 0.2V, 1.8V < VLX < 28V, VBST = VLX + 5V 180 -10 2.47 2.51 10 220 +10 V mV A mV 5.5V < VV+ < 28V, 1mA < ILOAD < 35mA Rising edge, typical hysteresis = 460mV 4.7 4.05 5.3 4.35 V V V+ = VL VV+ = 12V, VL unloaded, no MOSFETs connected, VFB = 0V 5.5 4.5 28.0 5.5 5.0 V V mA CONDITIONS MIN TYP MAX UNITS
CURRENT-LIMIT COMPARATOR (all current limits are tested at VV+ = VVL = 4.5V and 5.5V)
Dual Mode is a trademark of Maxim Integrated Products, Inc. 4 _______________________________________________________________________________________
Low-Dropout, Wide-Input-Voltage, Step-Down Controllers
ELECTRICAL CHARACTERISTICS (continued)
(VV+ = VVL = VAVL = VEN = VREFIN = 5V, VBST = 6V, VLX = 1V, CVL = 4.7F, CREFOUT = 1F, VAIN- = VAOUT, VAIN+ = 2.5V, VILIM = VLX - 0.2V, VFB = 0.65V, GND = PGND = 0V, CSS = 0.01F, RFREQ = 20k, TA = -40C to +85C, typical values are at TA = +25C, unless otherwise noted.) (Note 1)
PARAMETER FREQUENCY RFREQ = 100k Frequency DH Minimum Off-Time DH Minimum On-Time FB ERROR AMPLIFIER FB Input Bias Current FB Input Voltage Set Point FB Offset Error Error-Amp Open-Loop Voltage Gain Over load and line VREFIN = 1.25V and 2.5V, measured with respect to REFIN VCOMP = 1.2V to 2.4V 0.591 +20 72 150 0.606 -20 nA V mV dB RFREQ = 20.0k RFREQ = 14.3k 140 800 1100 180 240 1200 1700 230 140 ns ns kHz CONDITIONS MIN TYP MAX UNITS
MAX8597/MAX8598/MAX8599
UNCOMMITTED OPERATIONAL AMPLIFIER (MAX8597 only) Output Voltage Swing High Output Voltage Swing Low Input Offset Voltage Input Common-Mode Range (CMVR) DRIVERS DH On-Resistance in Low State DH On-Resistance in High State DL On-Resistance in Low State DL On-Resistance in High State BST Bias Current LX Bias Current BST/LX Leakage Current LOGIC INPUTS (EN) Input Low Level Input High Level Input Bias Current REFIN INPUT (MAX8597 only) REFIN Input Voltage Range REFIN Dual-Mode Threshold REFIN Input Bias Current VREFIN = 1.25V or 2.5V 0 VAVL 1.0 -250 2.75 VAVL 0.5 +250 V V nA 4.5V < VVL = VV+ = VAVL < 5.5V 4.5V < VVL = VV+ = VAVL < 5.5V VVL = VV+ = VAVL = 5.5V, VEN = 0 to 5.5V 2.4 -1 +1 0.8 V V A VBST - VLX = 5V VBST - VLX = 5V VVL = VV+ = 5V VVL = VV+ = 5V VBST = 33V, VLX = 28V, VEN = 0V VBST = 33V, VLX = 28V, VEN = 0V VBST = VLX = 28V, VEN = 0V 2.5 3.3 1.0 3.5 520 -520 50 A A A VAIN+ = 2.5V, VAIN- = (VAIN+ - 100mV), ISOURCE = 100A VAIN+ = 2.5V, VAIN- = (VAIN+ + 100mV), ISINK = 100A VCM = 1.25V and 2.5V -3 +0.50 VAVL 20mV 20 +3 VAVL 2.0 V mV mV V
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5
Low-Dropout, Wide-Input-Voltage, Step-Down Controllers MAX8597/MAX8598/MAX8599
ELECTRICAL CHARACTERISTICS (continued)
(VV+ = VVL = VAVL = VEN = VREFIN = 5V, VBST = 6V, VLX = 1V, CVL = 4.7F, CREFOUT = 1F, VAIN- = VAOUT, VAIN+ = 2.5V, VILIM = VLX - 0.2V, VFB = 0.65V, GND = PGND = 0V, CSS = 0.01F, RFREQ = 20k, TA = -40C to +85C, typical values are at TA = +25C, unless otherwise noted.) (Note 1)
PARAMETER OV AND UV FAULT COMPARATORS Upper FB Fault Threshold (OV) Lower FB Fault Threshold (UV) Lower FB POK Threshold POK Output Low Level POK Output High Leakage Rising edge, hysteresis = 15mV (MAX8599 only) Falling edge, hysteresis = 15mV FB falling, hysteresis = 20mV ISINK = 2mA VPOK = 5.5V 115 67 85 120 73 90 0.4 5 % % % V A CONDITIONS MIN TYP MAX UNITS
POWER-OK OUTPUT (POK) (MAX8598/MAX8599 only)
Note 1: Limits to -40C are guaranteed by design and characterization.
Typical Operating Characteristics
(Circuit of Figure 4, TA = +25C, 500kHz switching frequency, VIN = 12V, unless otherwise noted.)
EFFICIENCY vs. LOAD CURRENT CIRCUIT OF FIGURE 1
MAX8597 toc01
EFFICIENCY vs. LOAD CURRENT CIRCUIT OF FIGURE 2
VOUT = 3.3V 90 80 VOUT = 2.5V VOUT = 1.8V VOUT = 1.2V
MAX8597 toc02
OUTPUT VOLTAGE vs. LOAD CURRENT
MAX8597 toc03
100 95 90 EFFICIENCY (%) 85 80 75 70 65 60 0.1 1 LOAD CURRENT (A) VOUT = 11.5V VOUT = 9V VOUT = 6V
100
1.210
70 60 50 40 30
OUTPUT VOLTAGE (V) 100
1.205
EFFICIENCY (%)
1.200
1.195
1.190 1 10 LOAD CURRENT (A) 0 2 4 6 8 10 12 14 16 18 20 ILOAD (A)
10
OUTPUT VOLTAGE vs. INPUT VOLTAGE
MAX8597 toc04
POWER-UP WAVEFORMS
MAX8597 toc05
POWER-DOWN WAVEFORMS
MAX8597 toc06
1.210
VAVL
5V/div
VAVL
5V/div
OUTPUT VOLTAGE (V)
1.205 ILOAD = 0A 1.200 ILOAD = 20A VOUT 1.195 VIN 1.190 10.0 10.5 11.0 11.5 12.0 12.5 13.0 13.5 14.0 VIN (V) 2ms/div 2ms/div 10V/div VIN 10V/div 1V/div IOUT 1V/div ILX 10A/div ILX 10A/div
6
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Low-Dropout, Wide-Input-Voltage, Step-Down Controllers
Typical Operating Characteristics (continued)
(Circuit of Figure 4, TA = +25C, 500kHz switching frequency, VIN = 12V, unless otherwise noted.)
MAX8597/MAX8598/MAX8599
OUTPUT PREBIASED STARTUP
MAX8597 toc07
STARTUP/SHUTDOWN WITH EN (ILOAD = 20A)
MAX8597 toc08
VPOK VLX 10V/div 1.2V VOUT 1.0V 5V/div VOUT VIN VDL 1ms/div 5V/div VEN 2ms/div ILX
5V/div
10A/div
1V/div
5V/div
OUTPUT VOLTAGE vs. VADJ (VIN = 12V)
12 11 OUTPUT VOLTAGE (V) 10 9 8 7 6 5 4 0 1 2 3 VADJ (V) 4 5 6 CIRCUIT OF FIGURE 1 RLOAD = 1.2 VIN (AC-COUPLED) VCOMP VOUT
MAX8597 toc09
ENTERING DROPOUT WAVEFORMS CIRCUIT OF FIGURE 1
MAX8597 toc10
13
VLX
10V/div 11V
500mV/div
100mV/div
2s/div
HEAVY-DROPOUT WAVEFORMS CIRCUIT OF FIGURE 1
MAX8597 toc11
OUTPUT TRACKING REFIN
MAX8597 toc12
VLX
10V/div 11.9V 1ms RISE TIME
VREFIN VOUT 1V/div
VOUT
VREFIN VCOMP 500mV/div 5ms RISE TIME VIN (AC-COUPLED) 10s/div 500mV/div CIRCUIT OF FIGURE 3 1ms/div VOUT 1V/div
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Low-Dropout, Wide-Input-Voltage, Step-Down Controllers MAX8597/MAX8598/MAX8599
Typical Operating Characteristics (continued)
(Circuit of Figure 4, TA = +25C, 500kHz switching frequency, VIN = 12V, unless otherwise noted.)
50% LOAD STEP AT 5A/s
MAX8597 toc13
90% LOAD STEP AT 5A/s
MAX8597 toc14
VOUT (AC-COUPLED) VOUT (AC-COUPLED) 50mV/div 20A IOUT 10A IOUT
100mV/div
20A
2A
40s/div
40s/div
SHORT-CIRCUIT RESPONSE
MAX8597 toc15
OUTPUT OVERVOLTAGE PROTECTION
MAX8597 toc16
VOUT
1V/div VFB 500mV/div
IIN
2A/div
VDH ILX 10A/div VDL 4ms/div 10s/div
10V/div 5V/div
8
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Low-Dropout, Wide-Input-Voltage, Step-Down Controllers
Block Diagram
MAX8597/MAX8598/MAX8599
ILIM
MAX8597 MAX8598 MAX8599
FREQ OSC 1VP-P PWM CONTROL LOGIC
200A BST DH LX
VL 1/20 COUNTER DL PGND
REFERENCE
REFOUT (MAX8597)
AVL
BIAS VREG SOFT-START EN V+
COMP
EAMP
GND OVP (MAX8599)
VL 1.17 x VREG UVP
VL SS REFIN (MAX8597)
0.7 x VREG FB POK (MAX8598/ MAX8599) N
AOUT (MAX8597)
AIN+ (MAX8597) AIN(MAX8597)
0.88 x VREG
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9
Low-Dropout, Wide-Input-Voltage, Step-Down Controllers MAX8597/MAX8598/MAX8599
Pin Description
PIN MAX8597 1 2 3 4 MAX8598/ MAX8599 1 -- 2 3 NAME FUNCTION Filtered VL Input. Connect to VL through a 10 resistor. Bypass to GND with a 0.22F or larger ceramic capacitor. External Reference Input. FB tracks the voltage input to REFIN. Connect REFIN to AVL to use the internal 0.6V reference. Analog Ground. Connect to the exposed paddle and analog ground plane and then connect to PGND at the output ground. Soft-Start Programming Input. Connect a capacitor from SS to GND to set the soft-start time. See the Selecting the Soft-Start Capacitor section for details. Feedback Input. Connect to the center tap of an external resistor-divider to set the output voltage. Regulates to 0.6V for the MAX8598/MAX8599 and MAX8597 when REFIN is connected to AVL. Regulates to VREFIN (MAX8597) when using an external reference. Compensation Input. Connect to the required compensation network. See the Compensation Design section for details. Enable Input. Drive EN high to enable the IC. Drive low to shut down the IC. Internal Reference Output. REFOUT regulates to 2.5V and can source up to 1mA. REFOUT discharges to GND during UVLO. Input Supply Voltage for Internal VL Regulator. Connect to an input supply in the 4.5V to 28V range. Bypass to GND with a 1F or larger ceramic capacitor through a 3 resistor. Internal 5V Linear-Regulator Output. VL provides power for the internal MOSFET gate drivers. Bypass to PGND with a 1F or larger ceramic capacitor. VL is always enabled except in thermal shutdown. See the Internal 5V Linear Regulator section for details. Low-Side Gate-Driver Output. Connect to the gate of the synchronous rectifier. DL swings from PGND to VL. DL is held low during shutdown. Power Ground. Connect to the synchronous rectifier's source and PGND plane. Bootstrap Input Supply for the High-Side MOSFET Driver. Connect to the cathode of an external diode from VL and connect a 0.1F or larger capacitor from BST to LX. High-Side Gate-Driver Output. Connect to the gate of the high-side MOSFET. DH swings from LX to BST. DH is low (connected to LX) during shutdown. External Inductor Connection. LX is the low supply for the DH gate driver as well as the sense connection for the current-limit circuitry. Connect LX to the switched side of the inductor as well as the source of the high-side MOSFET and the drain of the synchronous rectifier. Current-Limit Sense Input. Connect a resistor from ILIM to the current-sense point to set the output current limit. See the Setting the Current Limit section for details.
AVL REFIN GND SS
5
4
FB
6 7 8 9
5 6 -- 7
COMP EN REFOUT V+
10
8
VL
11 12 13 14
9 10 11 12
DL PGND BST DH
15
13
LX
16
14
ILIM
10
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Low-Dropout, Wide-Input-Voltage, Step-Down Controllers
Pin Description (continued)
PIN MAX8597 17 18 19 20 -- -- MAX8598/ MAX8599 15 -- -- -- 16 -- NAME FUNCTION Frequency Adjust Input. Connect a resistor from FREQ to GND to set the switching frequency. The range of the FREQ resistor is 14.3k to 100k (corresponding to 1400kHz to 200kHz). Output of the Uncommitted Operational Amplifier. AOUT is high impedance during undervoltage lockout. Inverting Input of the Uncommitted Operational Amplifier Noninverting Input of the Uncommitted Operational Amplifier Power-OK Output. POK is an open-drain output that goes high impedance when the regulator output is greater than 88% of the regulation threshold. POK is low during shutdown. Exposed Paddle. Connect to analog ground plane for improved thermal performance.
MAX8597/MAX8598/MAX8599
FREQ AOUT AINAIN+ POK EP
Detailed Description
The MAX8597/MAX8598/MAX8599 voltage-mode PWM step-down controllers are designed to operate from 4.5V to 28V input and generate output voltages down to 0.6V. A proprietary switching algorithm stretches the duty cycle to >99.5% for low-dropout design. Unlike conventional step-down regulators using a p-channel high-side MOSFET to achieve high duty cycle, the MAX8597/MAX8598/MAX8599 drive n-channel MOSFETs permitting high efficiency and high-current designs. The MAX8597 is available in a 20-pin thin QFN package and is designed for applications that use an analog signal to control the output voltage with adjustable offset, such as DC fan speed control. For example, a 12VDC fan can be driven from 6V to 12V with 12V input power source depending on the system's cooling requirement to minimize fan noise and power consumption. This is achieved with an internal uncommitted operational amplifier. With the addition of an external RC filter, a PWM input can also be used to control the output voltage. The MAX8597 also generates a tracking output for chipsets, ASICs, and DSP where core and I/O supplies are split and require tracking. In applications where tighter output tolerance is required, the MAX8597 output can be set by an external precision reference source feeding to REFIN. The MAX8598/ MAX8599 are available in a 16-pin thin QFN package and do not have the uncommitted operational amplifier, reference input, and reference output, but offer a powerOK output (POK). With the enable input and POK output, the MAX8598/MAX8599 can easily be configured to have power sequencing of multiple supply rails.
The MAX8597/MAX8598/MAX8599 allow startup with prebias voltage on the output for applications where a backup supply or a tracking device may charge the output capacitor before the MAX8597/MAX8598/ MAX8599 are enabled. The MAX8599 has output overvoltage protection. These controllers feature lossless high-side peak inductor current sensing, adjustable current limit, and hiccup-mode short-circuit protection. Switching frequency is set with an external resistor from 200kHz to 1.4MHz. This wide frequency range combined with a wide-bandwidth error amplifier enable the loop-compensation scheme to give the user ample flexibility to optimize for cost, size, and efficiency.
DC-DC Controller
The MAX8597/MAX8598/MAX8599 step-down DC-DC controllers use a PWM voltage-mode control scheme. An internal high-bandwidth (25MHz) operational amplifier is used as an error amplifier to regulate the output voltage. The output voltage is sensed and compared with an internal 0.6V reference or REFIN (MAX8597) to generate an error signal. The error signal is then compared with a fixed-frequency ramp by a PWM comparator to give the appropriate duty cycle to maintain output voltage regulation. The high-side MOSFET turns on at the rising edge of the internal clock 20ns after DL (the low-side MOSFET gate drive) goes low. The high-side MOSFET turns off once the internal ramp voltage reaches the error-amplifier output voltage. The process repeats for every clock cycle. During the high-side MOSFET on-time, current flows from the input through the inductor to the output capacitor and load. At the moment the high-side MOSFET turns off, the energy stored in the inductor during the on-time is released to support the load as the inductor
11
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Low-Dropout, Wide-Input-Voltage, Step-Down Controllers MAX8597/MAX8598/MAX8599
current ramps down through the low-side MOSFET body diode; 20ns after DH goes low, the low-side MOSFET turns on, resulting in a lower voltage drop to increase efficiency. The low-side MOSFET turns off at the rising edge of the next clock pulse, and when its gate voltage discharges to zero, the high-side MOSFET turns on and another cycle starts. These controllers also sense peak inductor current and provide hiccup-overload and short-circuit protection (see the Current Limit section). The MAX8597/ MAX8598/MAX8599 operate in forced-PWM mode where the inductor current is always continuous. The controller maintains constant switching frequency under all loads, except under dropout conditions where it skips DL pulses.
High-Side Gate-Drive Supply (BST)
Gate-drive voltage for the high-side n-channel MOSFET is generated by an external flying capacitor and diode boost circuit (D1 and C5 in Figure 1). When the synchronous rectifier is on, C5 is charged from the VL supply through the Schottky diode. When the synchronous rectifier is turned off, the Schottky is reverse biased and the voltage on C5 is stacked above LX to provide the necessary turnon voltage for the high-side MOSFET. A low-current Schottky diode, such as Central Semiconductor's CMDSH-3, works well for most applications. The capacitor should be large enough to prevent it from charging to excessive voltage, but small enough to adequately charge during the minimum low-side MOSFET on-time, which occurs at minimum input voltage. A capacitor in the 0.1F to 0.47F range works well for most applications.
Current Limit
The MAX8597/MAX8598/MAX8599 DC-DC step-down controllers sense the peak inductor current either with the on-resistance of the high-side MOSFET for lossless sensing, or a series resistor for more accurate sensing. When the voltage across the sensing element exceeds the current-limit threshold set with ILIM, the controller immediately turns off the high-side MOSFET. The lowside MOSFET is then turned on to let the inductor current ramp down. As the output load current increases above the ILIM threshold, the output voltage sags because the truncated duty cycle is insufficient to support the load current. When FB falls 30% below its nominal threshold, the output undervoltage protection is triggered and the controller enters hiccup mode to limit power dissipation. This current-limit method allows the circuit to withstand a continuous output short circuit. The MAX8597/MAX8598/MAX8599 current-limit threshold is set by an external resistor that works in conjunction with an internal 200A current sink (see the Setting the Current Limit section for more details).
Internal 5V Linear Regulator
The MAX8597/MAX8598/MAX8599 contain a lowdropout 5V regulator that provides up to 35mA to supply gate drive for the external MOSFETs, and supplies AVL, which powers the IC's internal circuitry. Bypass the regulator's output (VL) with 1F per 10mA of VL load, or greater ceramic capacitor. The current required to drive the external MOSFET can be estimated by multiplying the total gate charge (at VGS = 5V) of the MOSFETs by the switching frequency.
Undervoltage Lockout (UVLO)
When V VL drops below 3.75V (typ), the MAX8597/ MAX8598/MAX8599s' undervoltage-lockout (UVLO) circuitry inhibits switching, forces POK (MAX8598/ MAX8599) low, and forces DH and DL low. Once VVL rises above 4.2V (typ), the controller powers up the output in startup mode (see the Startup section).
Startup
The MAX8597/MAX8598/MAX8599 start switching once all the following conditions are met: 1) EN is high. 2) VVL > 4.2V (typ). 3) Soft-start voltage VSS exceeds VFB. 4) Thermal limit is not exceeded. The third condition ensures that the MAX8597/ MAX8598/MAX8599 do not discharge a prebiased output. Once all of these conditions are met, the IC begins switching and the soft-start cycle is initiated.
Synchronous-Rectifier Driver (DL)
Synchronous rectification reduces the conduction loss in the rectifier by replacing the normal Schottky catch diode with a low-resistance MOSFET switch. The MAX8597/MAX8598/MAX8599 also use the synchronous rectifier to ensure proper startup of the boost gate-drive circuit.
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Low-Dropout, Wide-Input-Voltage, Step-Down Controllers
Power-OK Signal (POK, MAX8598/MAX8599 Only)
The power-OK signal (POK) is an open-drain output that goes high impedance when FB is above 91% of its nominal threshold. There is an eight clock-cycle delay before POK goes high impedance. For 500kHz switching frequency, this delay is typically 16s. To obtain a logic voltage output, connect a pullup resistor from POK to AVL. A 100k resistor works well for most applications. If unused, connect POK to GND or leave it unconnected. condition still exists, the UVP process begins again. The result is "hiccup" mode, where the controller attempts to restart periodically as long as the overload condition exists. In hiccup mode, the soft-start capacitor voltage ramps up to 112% of the nominal VFB threshold and then ramps down to 50mV. For the MAX8597, VREFIN must be greater than 450mV to trigger UVP. The softstart capacitor voltage then ramps up to 112% of VREFIN and then down to 50mV.
MAX8597/MAX8598/MAX8599
Enable and Soft-Start
The MAX8597/MAX8598/MAX8599 are enabled using the EN input. A logic high on EN enables the output of the IC. Conversely, a logic low on EN disables the output. On the rising edge of EN, the controllers enter softstart. Soft-start gradually ramps up the reference voltage seen at the error amplifier to control the output rate of rise and reduce the inrush current during startup. The soft-start period is determined by a capacitor connected from SS to GND (C6 in Figure 1). A 5A current source charges the external capacitor to the reference voltage (0.6V or VREFIN). The capacitor value is determined as follows: C6 = 5A x t SS VFB
Output Overvoltage Protection (OVP, MAX8599)
The output voltage is continuously monitored for overvoltage (MAX8599 only). If the output voltage is more than 117% of its nominal set value, OVP is triggered after a 12s (typ) delay. The MAX8599 latches DH low to turn off the high-side MOSFET, and DL high to turn on the low-side MOSFET to clamp the output to PGND. The latch is reset either by toggling EN or by cycling V+ below the UVLO threshold. Note that DL latching high causes a negative spike at the output due to the energy stored in the output LC at the instant of OVP trip. If the load cannot tolerate this negative spike, add a power Schottky diode across the output to act as a reverse polarity clamp.
Thermal-Overload Protection
Thermal-overload protection limits the total power dissipation in the MAX8597/MAX8598/MAX8599. When the junction temperature exceeds +160C, a thermal sensor shuts down the device, forcing DH and DL low, allowing the IC to cool. The thermal sensor turns the part on after the junction temperature cools by 10C, resulting in a pulsed output during continuous thermaloverload conditions. During a thermal event, the switching converter is turned off, the reference is turned off, the VL regulator is turned off, POK is high impedance, and the soft-start capacitor is discharged.
where tSS is the soft-start time in seconds and VFB is 0.6V or VREFIN. The output reaches regulation when soft-start is completed.
Output Undervoltage Protection (UVP)
Output UVP begins when the controller is at its current limit and VFB is 30% below its nominal threshold. This condition causes the controller to drive DH and DL low and discharges the soft-start capacitor with a 5A pulldown current until VSS reaches 50mV. Then the controller begins in soft-start mode. If the overload
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13
Low-Dropout, Wide-Input-Voltage, Step-Down Controllers MAX8597/MAX8598/MAX8599
Design Procedure
VIN (10.8V TO 13.2V) R15 3 C2A 10F VL C2B 10F C3 0.01F
R1 33.2k ON OFF R4 100k R5 32.4k EN AVL 2 7 REFIN EN AINAIN+ SS AOUT
C1 1F
VADJ (0V TO 5V) C15 0.01F
19 C6 0.033F 20 4
17 9 FREQ V+
16 ILIM BST 13
D1 CMDSH-3
R2 1.21k
DH
14 R16 3
Q1 IRF7821 C5 0.22F Q2 IRF7821 L1 1H R1 2 C7A 47F VOUT 6V TO 12V/10A C7B 47F
R6 48.7k R9 6.04k
18 R8 24.9k 5 C8 4.7pF R12 47k C9 820pF
MAX8597
LX DL
15 11 12
R7 48.7k
FB COMP GND 3 6 AVL 1 REFO 8
PGND VL 10
C14 2200pF C12 4.7F
R10 93.1k
R13 10
R11 5.1k C10 100pF
C11 0.22F
C13 1F
VL
Figure 1. MAX8597 (600kHz): Live Adjustable Output Voltage from 6V to 12V at 10A
VIN (10.8V TO 13.2V) R14 3 C2A 10F
R1 40.2k ON OFF R3 10k R4 10k R5 10k EN AVL 2 7 REFIN EN AIN-
C1 1F D1 CMDSH-3
VL C3 0.01F
C2B 10F
19
17 9 FREQ V+
16 ILIM BST DH
R2 1.65k
C2C 10F
13 14 R16 3 (Q1 = Q2 = C5 IRF7807Z) 0.22F
Q1
Q2
20 C4 0.033F 4 18
AIN+ LX 15
L1 0.7H Q3 Q4 R12 3 C7A 470F C7B 470F
VOUT 1.2V/20A
R6 10k R9 12.1k
MAX8597
SS AOUT FB COMP GND 3 6 AVL 1 REFO 8 DL 11 (Q3 = Q4 = IRF7832) 12
R7 12.1k R8 7.2k C8 1800pF
C13 2200pF
5 C8 39pF
PGND VL 10
R10 16k
C9 6800pF C10 0.22F
R11 10
C12 4.7F
C11 1F VL
Figure 2. 1.2V at 20A Output with Remote Sensing 14 ______________________________________________________________________________________
Low-Dropout, Wide-Input-Voltage, Step-Down Controllers
Design Procedure (continued)
VIN (10.8V TO 13.2V) R1 20k ON OFF EN REFIN R3 70k D2 CMPD914 R5 6.98k R4 18.2k C4 1000pF 19 20 C6 2200pF 4 SS D1 CMDSH-3 13 Q1 IRF7807Z R16 3 C5 0.22F Q2 IRF7821 L1 0.56H C7A R10 2 100F C14 2200pF C13 4.7F C7B 100F VOUT 1.8V/10A R2 1.5k C3 0.01F R12 3 C2A 10F VL C2B 10F
MAX8597/MAX8598/MAX8599
C1 1F
2 7 17 REFIN EN FREQ
9 V+
16 ILIM BST
AINAIN+
DH
14
MAX8597
LX DL PGND
15 11 12
18 5 R6 10k C8 56pF R8 5.6k C9 8200pF
AOUT FB COMP GND 3 6 AVL 1 REFO 8
R7 390 C10 1000pF
R9 10
VL 10
C11 0.22F
C12 1F
VL
Figure 3. MAX8597 1MHz Tracking Supply with Clamp (Output voltage tracks VREFIN from 0V up to the nominal output regulation voltage.)
VIN (10.8V TO 13.2V) R11 3 C2A 10F
R1 40.2k ON OFF EN AVL R3 100k 16 C4 0.033F 3 R4 12.1k C8 39pF R5 12.1k R6 1.2k C8 1800pF 5 R7 16k C9 6800pF AVL COMP GND 2 AVL 1 SS POK 6 EN
C1 1F D1 CMDSH-3
VL C3 0.01F
C2B 10F
15 FREQ
7 V+
14 ILIM BST DH 11 12 R16 3
R2 2.26k
C2C 10F
POK
C5 0.22F
Q1 HAT2168H L1 0.7H R9 3 C7A 470F C7B 470F VOUT 1.2V/20A
4
FB
MAX8598 MAX8599
LX
13
DL
9
Q2 HAT2165H
Q3 HAT2165H
C12 2200pF
VL 8 R8 10
PGND 10 C11 4.7F
C10 0.22F
VL
Figure 4. MAX8598/MAX8599 500kHz, 1.2V, 20A Output Power Supply ______________________________________________________________________________________ 15
Low-Dropout, Wide-Input-Voltage, Step-Down Controllers MAX8597/MAX8598/MAX8599
Setting the Output Voltage
Fixed Output Voltage The output voltage is set by a resistor-divider network from the output to GND with FB at the center tap (R4 and R5 in Figure 4). Select R4 between 5k and 15k and calculate R5 by: R5 = R4 x [( VOUT / VFB) - 1] Live Adjustable Output Voltage (see Figure 1) Using the uncommitted operational amplifier, the MAX8597 can be configured such that the output voltage is adjustable using a voltage source (VADJ). The following parameters must be defined before starting the design: * The minimum desired output voltage, VOUT_MIN * The maximum desired output voltage, VOUT_MAX * The desired input that corresponds to the minimum output voltage, VADJ_MIN * The desired input that corresponds to the maximum output voltage, VADJ_MAX Select VAOUT (uncommitted operational-amplifier output) between 0.05V and 3V and V AOUT_MAX higher than VAOUT_MIN. Calculate the required AIN+ reference (VAIN+) as:
VAIN+ = VAOUT _ MAX x VADJ _ MAX - VAOUT _ MIN x VADJ _ MIN (VADJ _ MAX - VADJ _ MIN ) + (VAOUT _ MAX - VAOUT _ MIN )
Additionally, to minimize error, R6 and R7 should be chosen such that: R6 x R7 R4 x R5 = R6 + R7 R4 + R5
Inductor Selection
There are several parameters that must be examined when determining which inductor is to be used: input voltage, output voltage, load current, switching frequency, and LIR. LIR is the ratio of inductor current ripple to DC load current. A higher LIR value allows for a smaller inductor but results in higher losses and higher output ripple. A good compromise between size and efficiency is a 30% LIR. Once all the parameters are chosen, the inductor value is determined as follows: L= VOUT x ( VIN - VOUT ) VIN x fS x ILOAD(MAX) x LIR
VAIN+ is set using a resistor-divider from REFOUT to GND (R6 and R7). Select R7 to be approximately 50k as a starting point and then calculate R6 as: R6 = R7 x [(2.5V / VAIN+) - 1] Select R4 to be 100k and calculate R5 as: R5 = (VAIN+
-
VAOUT _ MIN ) x R4
-
where fS is the switching frequency. Choose a standard value close to the calculated value. The exact inductor value is not critical and can be adjusted in order to make trade-offs among size, cost, and efficiency. Lower inductor values minimize size and cost, but also increase the output ripple and reduce the efficiency due to higher peak currents. On the other hand, higher inductor values increase efficiency, but eventually resistive losses due to extra turns of wire exceed the benefit gained from lower AC current levels. Find a lowloss inductor having the lowest possible DC resistance that fits the allotted dimensions. Ferrite cores are often the best choice, although powdered iron is inexpensive and can work well up to 300kHz. The chosen inductor's saturation current rating must exceed the peak inductor current determined as: LIR IPEAK = ILOAD(MAX) + x ILOAD(MAX) 2
(VADJ _ MAX
VAIN+ )
Select R9 between 5k and 15k, then calculate R8 and R10 as follows:
R8 =
Input Capacitor
The input filter capacitor reduces peak currents drawn from the power source and reduces noise and voltage ripple on the input caused by the circuit's switching. The input capacitor must meet the ripple current requirement (IRMS) imposed by the switching currents defined by the following equation: IRMS = ILOAD x VOUT x ( VIN - VOUT ) VIN
[(VOUT _ MIN
- VFB
) x (VFB - VAOUT _ MIN ) + (VOUT _ MAX - VFB ) x (VAOUT _ MAX - VFB )] x R9 ((VOUT _ MAX - VFB ) - (VOUT _ MIN - VFB )) x VFB
R8 x R9 x VOUT _ MAX - VFB
R10 =
(VFB x R8) + [(VFB - VAOUT _ MIN ) x R9]
(
)
where VFB is the feedback regulation voltage (0.6V with REFIN connected to AVL).
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Low-Dropout, Wide-Input-Voltage, Step-Down Controllers
I RMS has a maximum value when the input voltage equals twice the output voltage (VIN = 2 x VOUT), so IRMS(MAX) = ILOAD / 2. Ceramic capacitors are recommended due to their low ESR and ESL at high frequency, with relatively lower cost. Choose a capacitor that exhibits less than 10C temperature rise at the maximum operating RMS current for optimum long-term reliability.
MOSFET Selection
The MAX8597/MAX8598/MAX8599 controllers drive external, logic-level, n-channel MOSFETs as the circuitswitch elements. The key selection parameters are: * On-resistance (RDS(ON)): the lower, the better. * Maximum drain-to-source voltage (VDSS): should be at least 20% higher than the input supply rail at the high-side MOSFET's drain. * Gate charges (Qg, Qgd, Qgs): the lower, the better. Choose MOSFETs with RDS(ON) rated at VGS = 4.5V. For a good compromise between efficiency and cost, choose the high-side MOSFET that has conduction loss equal to the switching loss at the nominal input voltage and maximum output current. For the low-side MOSFET, make sure it does not spuriously turn on due to dv/dt caused by the high-side MOSFET turning on, resulting in efficiency degrading shoot-through current. MOSFETs with a lower Qgd/Qgs ratio have higher immunity to dv/dt. For proper thermal-management design, the power dissipation must be calculated at the desired maximum operating junction temperature, maximum output current, and worst-case input voltage (for low-side MOSFET, worst case is at VIN(MAX); for high-side MOSFET, it could be either at VIN(MIN) or VIN(MAX)). High-side and low-side MOSFETs have different loss components due to the circuit operation. The low-side MOSFET operates as a zero-voltage switch; therefore, the major losses are the channel-conduction loss (PLSCC) and the body-diode conduction loss (PLSDC): PLSCC = [1 - (VOUT / VIN)] x (ILOAD)2 x RDS(ON) PLSDC = 2 x ILOAD x VF x tdt x fS where VF is the body-diode forward-voltage drop, tdt is the dead-time between the high-side MOSFET and the low-side MOSFET switching transitions, and fS is the switching frequency. The high-side MOSFET operates as a duty-cycle control switch and has the following major losses: the channel-conduction loss (PHSCC), the V-I overlapping switching loss (PHSSW), and the drive loss (PHSDR). The high-side MOSFET does not have body-diode conduction loss because the diode never conducts current: PHSCC = (VOUT / VIN) x ILOAD2 x RDS(ON) Use RDS(ON) at TJ(MAX): PHSSW = VIN x ILOAD x fS x [(Qgs + Qgd) / IGATE] where IGATE is the average DH-high driver output-current capability determined by: IGATE = 2.5 / (RDH + RGATE)
MAX8597/MAX8598/MAX8599
Output Capacitor
The key selection parameters for the output capacitor are the actual capacitance value, the equivalent series resistance (ESR), the equivalent series inductance (ESL), and the voltage-rating requirements, which affect the overall stability, output ripple voltage, and transient response. The output ripple has three components: variations in the charge stored in the output capacitor, voltage drop across the capacitor's ESR, and voltage drop across the capacitor's ESL, caused by the current into and out of the capacitor. The following equations estimate the worst-case ripple: VRIPPLE = VRIPPLE(ESR) + VRIPPLE(ESL) + VRIPPLE(C) VRIPPLE(ESR) = IP-P x ESR V x ESL VRIPPLE(ESL) = IN L + ESL IP-P VRIPPLE(C) = 8 x COUT x fS V -V V IP-P = IN OUT x OUT fS x L VIN where IP-P is the peak-to-peak inductor current. The response to a load transient depends on the selected output capacitor. After a load transient, the output instantly changes by (ESR x ILOAD) + (ESL x di/dt). Before the controller can respond, the output deviates further depending on the inductor and output capacitor values. After a short period of time (see the Typical Operating Characteristics), the controller responds by regulating the output voltage back to its nominal state. The controller response time depends on the closedloop bandwidth. With higher bandwidth, the response time is faster, preventing the output capacitor voltage from further deviation from its regulation value. Do not exceed the capacitor's voltage or ripple current ratings.
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17
Low-Dropout, Wide-Input-Voltage, Step-Down Controllers MAX8597/MAX8598/MAX8599
where RDH is the high-side MOSFET driver's average on-resistance (1.25 typ) and RGATE is the internal gate resistance of the MOSFET (typically 0.5 to 2): PHSDR = Qgs x VGS x fS x RGATE / (RGATE + RDH) where VGS ~ VVL = 5V. In addition to the losses above, add approximately 20% more for additional losses due to MOSFET output capacitances and low-side MOSFET body-diode reverse-recovery charge dissipated in the high-side MOSFET that exists, but is not well defined in the MOSFET data sheet. Refer to the MOSFET data sheet for thermal-resistance specification to calculate the PC board area needed to maintain the desired maximum operating junction temperature with the abovecalculated power dissipation. To reduce EMI caused by switching noise, add a 0.1F or larger ceramic capacitor from the high-side switch drain to the lowside switch source or add resistors in series with DH and DL to slow down the switching transitions. However, adding a series resistor increases the power dissipation of the MOSFETs, so be sure this does not overheat the MOSFETs. The minimum load current must exceed the high-side MOSFET's maximum leakage plus the maximum LX bias current over temperature. the LX voltage waveform can interfere with the current limit. Below is the procedure for selecting the value of the series RC snubber circuit (R14 and C14 in Figure 1): 1) Connect a scope probe to measure VLX to GND, and observe the ringing frequency, fR. 2) Find the capacitor value (connected from LX to GND) that reduces the ringing frequency by half. The circuit parasitic capacitance (CPAR) at LX is then equal to 1/3 the value of the added capacitance above. The circuit parasitic inductance (LPAR) is calculated by: LPAR = 1
(2 x fR )2 x CPAR
The resistor for critical dampening (R14) is equal to 2 x fR x LPAR. Adjust the resistor value up or down to tailor the desired damping and the peak voltage excursion. The capacitor (C14) should be at least 2 to 4 times the value of the CPAR in order to be effective. The power loss of the snubber circuit is dissipated in the resistor (R14) and is calculated as: PR14 = C14 x (VIN)2 x fS where VIN is the input voltage and fS is the switching frequency. Choose an R14 power rating that meets the specific application's derating rule for the power dissipation calculated. Additionally, there is parasitic inductance of the current-sensing element, whether the high-side MOSFET (L SENSE_FET ) or the optional current-sense resistor (LRSENSE) are used, which is in series with the output filter inductor. This parasitic inductance, together with the output inductor, forms an inductive divider and causes error in the current-sensing voltage. To compensate for this error, a series RC circuit can be added in parallel with the sensing element (see Figure 5). The RC time constant should equal LRSENSE / RSENSE, or LSENSE_FET / RDS(ON). First, set the value of R equal to or less than R2 / 100. Then, the value of C is calculated as: C = LRSENSE / (RSENSE x R) or C = LSENSE_FET / (RDS(ON) x R) Any PC board trace inductance in series with the sensing element and output inductor should be added to the specified FET or resistor inductance per the respective manufacturer's data sheet. For the case of
Setting the Current-Limit
The MAX8597/MAX8598/MAX8599 controllers sense the peak inductor current to provide constant-current and hiccup current limit. The peak current-limit threshold is set by an external resistor (R2 in Figure 1) together with the internal current sink of 200A. The voltage drop across the resistor R2 due to the 200A current sets the maximum peak inductor current that can flow through the high-side MOSFET or the optional currentsense resistor (between the high-side MOSFET source and LX) by the equations below: IPEAK(MAX) = 200A x R2 / RDSON(HSFET) IPEAK(MAX) = 200A x R2 / RSENSE The actual corresponding maximum load current is lower than the IPEAK(MAX) by half of the inductor ripple current. If the RDS(ON) of the high-side MOSFET is used for current sensing, use the maximum RDS(ON) at the highest operating junction temperature to avoid false tripping of the current limit at elevated temperature. Consideration should also be given to the tolerance of the 200A current sink. When the RDS(ON) of the highside MOSFET is used for current sensing, ringing on
18
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Low-Dropout, Wide-Input-Voltage, Step-Down Controllers MAX8597/MAX8598/MAX8599
R2 ILIM DH C3 DH LX LX DL DL RDS(ON) R C3 C RSENSE R C
R2 ILIM
Figure 5. Adding RC for More Accurate Sensing
the MOSFET, it is the inductance from the drain to the source lead. Alternately, to save board space and cost, the RC networks above can be omitted; however, the value of RILIM should be raised to account for the voltage step caused by the inductive divider. An additional switching noise filter may be needed at ILIM by connecting a capacitor in parallel with R2 (in the case of RDS(ON) sensing) or from ILIM to LX (in the case of resistor sensing). For the case of RDS(ON) sensing, the value of the capacitor should be: C3 > 15 / ( x fS x R2) For the case of resistor sensing: C3 < 25 x 10-9 / R2
Selecting the Soft-Start Capacitor
An external capacitor from SS to GND is charged by an internal 5A current source, to the corresponding feedback threshold. Therefore, the soft-start time is calculated as: tSS = CSS x VFB / 5A For example, 0.033F from SS to GND yields approximately a 3.96ms soft-start period. In the tracking application (see Figure 3), the output voltage is required to track REFIN during REFIN rise and fall time. CSS must be chosen so that tss is less than REFIN rise and fall time.
comparing the error-amplifier output (COMP) with a fixed internal ramp to produce the required duty cycle. The error amplifier is an operational amplifier with 25MHz bandwidth to provide fast response. The output lowpass LC filter creates a double pole at the resonant frequency that introduces a gain drop of 40dB per decade and a phase shift of 180 degrees per decade. The error amplifier must compensate for this gain drop and phase shift to achieve a stable high-bandwidth closed-loop system. The Type III compensation scheme (Figure 6) is used to achieve this stability. The basic regulator loop can be thought of as consisting of a power modulator and an error amplifier. The power modulator has a DC gain set by VIN / VRAMP, with a double pole, fP_LC, and a single zero, fZ_ESR, set by the output inductor (L), the output capacitor (CO), and its equivalent series resistance (RESR). Below are the equations that define the power modulator: GMOD(DC) = fP _ LC = fZ _ ESR = VIN , where VRAMP = 1V (typ) VRAMP 1 1 2 x RESR x CO
2 L x C O
Compensation Design
The MAX8597/MAX8598/MAX8599 use a voltage-mode control scheme that regulates the output voltage by
where CO is the total output capacitance and RESR is the total ESR of the output capacitors.
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19
Low-Dropout, Wide-Input-Voltage, Step-Down Controllers MAX8597/MAX8598/MAX8599
When the output capacitor is comprised of paralleling n number of the same capacitors, then: CO = n x CEACH and RESR = RESR_EACH / n Thus, the resulting fZ_ESR is the same as that of a single capacitor. The total closed-loop gain must be equal to unity at the crossover frequency, where the crossover frequency is less than or equal to 1/5 the switching frequency (fS): fC fS / 5 So the loop-gain equation at the crossover frequency is: GEA(FC) x GMOD(FC) = 1 where GEA(FC) is the error-amplifier gain at fC, and GMOD(FC) is the power-modulator gain at fC. The loop compensation is affected by the choice of output filter capacitor due to the position of its ESR-zero frequency with respect to the desired closed-loop crossover frequency. Ceramic capacitors are used for higher switching frequencies and have low capacitance and low ESR; therefore, the ESR-zero frequency is higher than the closed-loop crossover frequency. Electrolytic capacitors (e.g., tantalum, solid polymer, and OS-CON) are needed for lower switching frequencies and have high capacitance (and some have higher ESR); therefore, the ESR-zero frequency can be lower than the closed-loop crossover frequency. Thus, the compensation design procedures are separated into two cases: Case 1: Crossover frequency is less than the output-capacitor ESR-zero (fC < fZ_ESR). The modulator gain at fC is: GMOD(FC) = GMOD(DC) x (fP_LC / fC)2 Since the crossover frequency is lower than the output capacitor ESR-zero frequency and higher than the LC double-pole frequency, the error-amplifier gain must have a +1 slope at fC so that, together with the -2 slope of the LC double pole, the loop crosses over at the desired -1 slope. The error amplifier has a dominant pole at a very low frequency (~0Hz), and two additional zeros and two additional poles as indicated by the equations below and illustrated in Figure 7: fZ1_EA = 1 / (2 x R4 x C2) fZ2_EA = 1 / (2 x (R1 + R3) x C1) fP2_EA = 1 / (2 x R3 x C1) fP3_EA = 1 / (2 x R4 x (C2 x C3 / (C2 + C3))) Note that fZ2_EA and fP2_EA are chosen to have the converter closed-loop crossover frequency, fC, occur when the error-amplifier gain has +1 slope, between fZ2_EA and fP2_EA. The error-amplifier gain at fC must meet the requirement below: GEA(FC) = 1 / GMOD(FC) The gain of the error amplifier between f Z1_EA and fZ2_EA is:
GEA(fZ1_EA - fZ2_EA) = GEA(FC) x fZ2_EA / fC = fZ2_EA / (fC x GMOD(FC))
This gain is set by the ratio of R4/R1 (Figure 6), where R1 is calculated as illustrated in the Setting the Output Voltage section. Thus: R4 = R1 x fZ2_EA / (fC x GMOD(FC)) where fZ2_EA = fP_LC. Due to the underdamped (Q > 1) nature of the output LC double pole, the first error-amplifier zero frequency must be set less than the LC double-pole frequency in order to provide adequate phase boost. Set the erroramplifier first zero, fZ1_EA, at 1/4 of the LC double-pole frequency. Hence: C2 = 2 / ( x R4 x fP_LC) Set the error amplifier fP2_EA at fZ_ESR and f f fp3 _ EA at s if fZ _ ESR is less than s . 2 2 fs If fZ _ ESR is greater than , then set 2 fs fp2 _ EA at and fp3 _ EA at fZ _ ESR. 2 The error-amplifier gain between fP2_EA and fP3_EA is set by the ratio of R4/RM and is equal to: GEA(fZ1_EA - fZ2_EA) x (fP2_EA / fP_LC) where RM = R1 x R3 / (R1 + R3). Then: RM = R4 x fP_LC / (GEA(fZ1_EA - fZ2_EA) x fP2_EA) = R4 x fC x GMOD(FC) / fP2_EA The value of R3 can then be calculated as: R3 = R1 x RM / (R1 - RM) Now we can calculate the value of C1 as: C1 = 1 / (2 x R3 x fp2_EA) and C3 as: C3 = C2 / ((2 x C2 x R4 x fP3_EA) - 1)
20
______________________________________________________________________________________
Low-Dropout, Wide-Input-Voltage, Step-Down Controllers
Case 2: Crossover frequency is greater than the output-capacitor ESR zero (fC > fZ_ESR). The modulator gain at fC is: GMOD(FC) = GMOD(DC) x (fP_LC)2 / (fZ_ESR x fC) Since the output-capacitor ESR-zero frequency is higher than the LC double-pole frequency but lower than the closed-loop crossover frequency, where the modulator already has -1 slope, the error-amplifier gain must have zero slope at fC so the loop crosses over at the desired -1 slope. The error-amplifier circuit configuration is the same as case 1 above; however, the closed-loop crossover frequency is now between fP2 and fP3 as illustrated in Figure 8. The equations that define the error amplifier's zeros (f Z1_EA , f Z2_EA ) and poles (f P2_EA , f P3_EA ) are the same as case 1; however, fP2_EA is now lower than the closed-loop crossover frequency. Therefore, the erroramplifier gain between fZ1_EA and fZ2_EA is now calculated as:
GEA(fZ1_EA - fZ2_EA) = GEA(FC) x fZ2_EA / fP2_EA = fZ2_EA / (fP2_EA x GMOD(FC))
Set the error-amplifier third pole, fP3_EA, at half the switching frequency, and let RM = (R1 x R3) / (R1 + R3). The gain of the error amplifier between fP2_EA and f P3_EA is set by the ratio of R4/RM and is equal to GEA(FC) = 1 / GMOD(FC). Then: RM = R4 x GMOD(FC) Similar to case 1, R3, C1, and C3 are calculated as: R3 = R1 x RM / (R1 - RM) C1 = 1 / (2 x R3 x fZ_ESR) C3 = C2 / ((2 x C2 x R4 x fP3_EA) - 1)
MAX8597/MAX8598/MAX8599
GAIN (dB)
CLOSED-LOOP GAIN
EA GAIN
This gain is set by the ratio of R4/R1, where R1 is calculated as illustrated in the Setting the Output Voltage section. Thus: R4 = R1 x fZ2_EA / (fP2_EA x GMOD(FC)) where fZ2_EA = fP_LC and fP2_EA = fZ_ESR. Similar to case 1, C2 is calculated as: C2 = 2 / ( x R4 x fP_LC)
0
fZ1
fZ2
fC
fP2
fP3
FREQUENCY
Figure 7. Closed-Loop and Error-Amplifier Gain Plot for Case 1
L CO
GAIN (dB)
MAX8597 MAX8598 MAX8599
R3 COMP C2 C1 R1
CLOSED-LOOP GAIN EA GAIN
C3
R4
R2
FB REF
0 fZ1 fZ2 fP2 fC fP3 FREQUENCY
Figure 6. Type III Compensation Network
Figure 8. Closed-Loop and Error-Amplifier Gain Plot for Case 2
______________________________________________________________________________________
21
Low-Dropout, Wide-Input-Voltage, Step-Down Controllers MAX8597/MAX8598/MAX8599
Applications Information
PC Board Layout Guide
Careful PC board layout is critical to achieve low switching losses and clean, stable operation. The switching power stage requires particular attention. Follow these guidelines for good PC board layout: 1) Place the high-side MOSFET close to the low-side MOSFET and arrange them in such a way that the drain of the high-side MOSFET and the source of the low-side MOSFET can be tightly decoupled with a 10F or larger ceramic capacitor. The MOSFETs should also be placed close to the controller IC, preferably not more than 1.5in away from the IC. 2) Place the IC's pin decoupling capacitors as close to pins as possible. 3) A current-limit setting resistor must be connected from ILIM directly to the drain of the high-side MOSFET. 4) Try to keep the LX node connection to the IC pin separate from the connection to the flying boost capacitor. 5) Keep the power ground plane (connected to the source of the low-side MOSFET, PGND pin, input and output capacitors' ground, VL decoupling ground) and the signal ground plane (connected to GND pin and the rest of the circuit ground returns) separate. Connect the two ground planes together at the ground of the output capacitor(s). 6) Place the RC snubber circuit as close to the lowside MOSFET as possible. 7) Keep the high-current paths as short as possible. 8) Connect the drains of the MOSFETs to a large copper area to help cool the devices and further improve efficiency and long-term reliability. 9) Ensure the feedback connection is short and direct. Place the feedback resistors as close to the IC as possible. 10) Route high-speed switching nodes, such as LX, DH, and DL away from sensitive analog areas (FB, COMP, ILIM, AIN+, AIN-). Refer to the MAX8597/MAX8598/MAX8599 evaluation kit for a sample board layout.
Pin Configurations (continued)
PGND BST TOP VIEW DH 12 LX 13
Chip Information
TRANSISTOR COUNT: 4493 PROCESS: BiCMOS
11
10
DL 9 8 VL
ILIM
14
7
V+
FREQ
15
MAX8598 MAX5899
6
EN
POK
16 1 AVL 2 GND 3 SS 4 FB
5
COMP
THIN QFN 4mm x 4mm
22
______________________________________________________________________________________
Low-Dropout, Wide-Input-Voltage, Step-Down Controllers
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
MAX8597/MAX8598/MAX8599
PACKAGE OUTLINE 12, 16, 20, 24L THIN QFN, 4x4x0.8mm
21-0139
C
1
2
______________________________________________________________________________________
24L QFN THIN.EPS
23
Low-Dropout, Wide-Input-Voltage, Step-Down Controllers MAX8597/MAX8598/MAX8599
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
PACKAGE OUTLINE 12, 16, 20, 24L THIN QFN, 4x4x0.8mm
21-0139
C
2
2
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
24 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2004 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

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